A prior art memory cell is shown in FIG. 1. The memory cell includes a first inverter IA and a second inverter IB connected upside down to each other between a first node A and a second node B, and a first access transistor TA having a drain connected to a first node A, a gate connected to a word line WL and a source connected to a bit line BLT. It also has a second access transistor TB having a drain connected to the second node B, a gate connected to the word line WL and a source connected to a second bit line BLF.
FIG. 2 illustrates N+1 memory cells P0, P1, . . . , PN as described here above, associated to form a row of a prior art SRAM memory, the row also comprising a differential read amplifier SA. All the cells P0, P1, . . . , PN are connected to the same bit rows BLF and BLT. However, each cell is connected to a different word line WL0, WL1, . . . , WLN. The amplifier SA is a differential amplifier. It has two differential inputs respectively connected to the first bit line and the second bit line.
To program a memory cell of the row of cells, a potential VDD is applied to the word line WL associated with the cell to be programmed and, depending on the piece of data, 0 or 1, to be programmed in the memory cell, a zero potential (ground connection) or the potential VDD is applied to the first bit line BLT, and a potential is applied to the line BLF that is the inverse of the potential applied to the line BLT. In one example, to program a logic 0 in the cell P0, VDD is applied to the lines WL0, BLF and the line BLT is connected to ground. After the programming of a 0, the cell A is at the 0 potential and the cell B is at the potential VDD.
To read the content of a memory cell, for example that of the cell P0 in FIG. 2, the two bit lines BLF and BLT are first of all pre-charged at a power supply potential VDD. Then, the potential VDD is applied to the corresponding word line WL0 (WL0=logic 1) to select the cell P0 (the other word lines are ground-connected: WL1= . . . =WLN=0) and the two bit lines BLF and BLT are made floating. Since the line WL0 is at the potential VDD, the access transistors TA0, TB0 of the memory cell P0 are on. Furthermore, since the node A0 of the cell P0 is at 0 and the line BLT is at the potential VDD, the two sides of the channel of the transistor TA0 are at a different potential, so that a current IREAD flows in this channel. This current IREAD will discharge the line BLT and thus gradually bring its potential to 0. However, since the node B0 of the cell P0 and the line BLF are at the same potential VDD, the two sides of the channel of the transistor TB0 are at the same potential and no current flows in this channel. The line BLF remains at the potential VDD. At the end of a certain period of time, the amplifier SA in principle detects a difference in potential between the lines BLT, BLF and accordingly produces a piece of data corresponding to the piece of data stored in the memory cell, i.e. a logic 0 if the potential at the line BLF is greater than the potential at the line BLT (this is the case of the cell P0 in FIG. 1), else a logic 1.
The reading is possible only if a potential difference of sufficient amplitude appears between the lines BLT and BLF. Now, because of leaks inherent in the access transistors TA, TB of the memory cells of the row, it is possible that this potential difference will never be sufficient, so that it will not be possible to read a cell accurately.
Indeed, even when it is properly turned off by an appropriate potential applied to its gate, a transistor shows leaks when a difference in potential appears between its drain and its source. In the example of FIG. 2, it is assumed that logic 1 values are stored in the cells P1, . . . , PN: the nodes A1, . . . , AN are thus at 1 and the nodes B1, . . . , BN are at 0. With the cell P0 being selected (WL0=1, the transistors TB1, TBN are off (WL1=0, WLN=0); despite this, leakage currents IOFF1, . . . , IOFFN are set up between the drain and the source of the transistors TB1, . . . , TBN. These currents IOFF are related to the potential difference between the line BLF and the cells TB1, . . . , TBN, and to the leakages inherent in the transistors TB1, TBN. They are identical if the transistors TB1, TBN are identical. They will together gradually discharge the potential of the line BLF. Assuming the worst case, if all the cells P1, . . . , PN store a logic 1, then a current equal to N*IOFF discharges the potential of the line BLF.
Although useful, this prior art SRAM memory cell configuration is not without its shortcomings. One shortcoming is if the current N*IOFF is close to the current IREAD, then the two lines BLT and BLF will get discharged simultaneously and along a similar slope so that the difference in potential between these two lines will never be great enough to enable accurate reading of the content of the memory cell P0.
In order to accommodate this shortcoming, it can be seen in practice that it is necessary to have IREAD/(N*IOFF) greater than 5 to enable accurate reading of a cell of the row of N memory cells. Since the current IOFF cannot be limited (it is inherent to the access transistors), it is necessary to limit the number N of cells associated with the same read amplifier SA to be able to ensure accurate reading of the content of the memory cells. It is therefore necessary either to limit the total number of memory cells of a SRAM memory (which obviously limits its capacity), or to add read amplifiers, leading to an increase in the size (in terms of surface area and volume of silicon occupied) of the memory. By way of an indication, for certain memories, N is limited to 128.
Accordingly, a need exists to overcome the shortcomings of the prior art and to provide a SRAM memory design with improved leakage current characteristics.